As is well known, dynamic random access memories (DRAMs) are so named because their cells can retain information only temporarily even with power continuously applied. The cells must therefore be read and refreshed at periodic intervals. Storage time is long enough to allow for many memory operations between refresh cycles. The advantages of cost per bit, device density, and flexibility of use have made DRAMs a widely used form of semiconductor memory.
The use of DRAM devices in integrated circuit designs has grown extensively over the years. Likewise, the density of the number of DRAM devices within certain integrated circuits has also increased substantially over the last few years. As device sizes have decreased, this has allowed manufacturers to increase the DRAM density even more. Along with the increase use of DRAM devices, however, a number of problems arose.
One such problem was the parasitic effect associated with operation of the DRAM device. Because of the smaller device size and the high operating currents due to large size of DRAM array, eddy currents would form within the P substrate. These eddy currents were highly undesirable because they caused the device to be inefficient. Furthermore, the eddy currents increased operating temperatures, which shortened the useful life of the device. To address this problem, manufactures inserted a buried oxide, which is often referred to as silicon on insulator (SOI). The SOI layer isolated the P-tub or N-tub from the substrate and thereby decreased the parasitic effect.
Although it has been found that the SOI somewhat decreases Ioff with some degree of success, the Ioff needs to be further reduced for the DRAM application. This high Ioff requirement in DRAMs can cause many problems related to heat transfer and hot carrier effects as well as more heat dissipation. Moreover, DRAMS are more temperature sensitive, and the increased temperature that accompanies larger current flows can damage the integrated circuit in which the DRAM device is located. Furthermore, a higher transistor Ioff can also lead to reduce the data storage time. This requires more frequent refresh-cycle time, resulting in a large power consumption.
There have been many attempts to reduce this excessively high Ioff. One such attempt calls for constructing a transistor without an n+ source and drain region. However, devices of this type are undesirable since they require a narrow process margin and additional masks. Moreover, leakage and degradation of transistor Ion may result. Another attempt has been to dope the SOI with n-type dopants. However, this has produced undesirable results in that the dopants caused leakage within the active layer. While these attempts have been directed to a lower transistor Ioff, this result is not always guaranteed. Many of the mentioned problems could be solved if a lower transistor Ioff in DRAMS is guaranteed.
Accordingly, what is needed in the art is a DRAM transistor that can be reliably manufactured, and a DRAM transistor that requires a lower transistor Ioff under a wide variety of process conditions. The present invention addresses this need.